Since self-aligned contacts (SAC) are used recent years because of micro patterning requirements, side wall spacers of silicon nitride film are used. A silicon nitride film is an insulating film with a barrier function capable of functioning as an etching stopper having etching selectivity relative to an interlayer insulating film made of a silicon oxide film.
Device sizes are reduced due to high integration and miniaturization of MOSFETs. As the pn junction depth of source/drain regions becomes shallow, resistance values have a tendency of becoming large. In order to reduce the resistance of the source/drain regions, it is effective to form silicide layers on the source/drain regions.
FIGS. 7A to 7E are cross sectional views illustrating main processes of a conventional semiconductor device manufacture method.
As shown in FIG. 7A, an isolation trench is formed in the surface layer of a silicon substrate 11 by etching, and an insulator is embedded in the trench to form a shallow trench isolation (STI) 12. Local oxidation of silicon (LOCOS) may be used instead of STI. The surfaces of active regions defined by the isolation region are thermally oxidized to form gate oxide films 13. A polysilicon film is deposited on the gate oxide film 13 by chemical vapor deposition (CVD) and etched by using a resist pattern to form a gate electrode 14.
In etching the gate electrode 14, mixture gas of HBr and Cl2 is used as etching gas to perform reactive etching which provides a high selection ratio between greatly different etching rates of silicon and the silicon oxide film. This etching provides an etching rate of the silicon oxide film very slower than that of silicon. Therefore, while polysilicon is etched, the gate oxide film 13 is etched only slightly and etching stops. Etching the polysilicon film is terminated in the state that the gate oxide film 13 is left on the surface of the active region. Damages are therefore hard to be formed in the surface layer of the active regions.
For example, n-type impurity ions are implanted by using the patterned gate electrode 14 as a mask to form extension regions 15 of source/drain regions. The extension regions 15 are formed to have a shallow junction depth in order to prevent punch-through.
As shown in FIG. 7B, a silicon nitride film is deposited by CVD, covering the gate electrode 14, and etched-back to remove the silicon nitride film on flat surfaces. Side wall spacers 16 of the silicon nitride film are left only on the side walls of the gate electrode 14. By using CHF3 as main etching gas, etching can be stopped in the state that the gate oxide film 13 is left. Therefore, it is possible to prevent damages from being formed in the active region surface.
As shown in FIG. 7C, the gate oxide film 13 exposed on both sides of the side wall spacers is removed by using dilute hydrofluoric acid solution. The side wall spacers 16 of silicon nitride are not etched. In this case, not only the exposed gate oxide film 13 is removed, but also the gate oxide film 13 under the side wall spacers 16 are laterally etched and retracted toward the gate electrode direction. Therefore, the side wall spacers 16 have an overhang shape.
As shown in FIG. 7D, by using the gate electrode 14 and side wall spacers 16 as a mask, for example, n-type impurity ions are implanted to form source/drain regions 17 having deep junction depth. In the above manner, the fundamental structure of a MOSFET is formed.
As shown in FIG. 7E, after the source and drain regions 17 are formed, metal capable of being silicidated such as Ti and Co is deposited on the substrate surface by sputtering. After a primary silicidation reaction is performed and unreacted metal is removed, secondary silicidation reaction is performed to form silicide layers 18 on the source/drain region surfaces and gate electrode surface.
An interlayer insulating film 21 of silicon oxide or the like is deposited on the substrate surface by CVD, covering the gate electrode. Contact holes are formed through the interlayer insulating film 21, and a Ti layer, and a TiN layer or the like are formed by sputtering and a W layer is deposited by CVD to bury the metal layer in the contact holes. An unnecessary metal layer is removed to form conductive plugs 22.
During the dilute hydrofluoric acid solution process, undercuts are formed under the silicon nitride side wall spacers 16 as shown in FIG. 7C. If metal enters the undercuts in a later process and left unremoved, the remaining metal may cause a short circuit. If the silicide layer is formed in the undercuts, the silicide layer may increase its volume and impart a stress to the side wall spacers 16.
Publication JP-A-HEI-9-162396 teaches a method of forming source/drain regions and discloses a laminated side wall spacer structure having nitride film side wall spacers covering the side walls of a gate electrode and a gate insulating film and oxide film side wall spacers formed on the nitride side wall spacers, as the side wall spacers of the gate electrode. Since the oxide film side wall spacers are formed on the whole surfaces of the nitride film side wall spacers, it can be considered that undercuts described above are not formed. However, since the nitride film side wall spacers contact the substrate surfaces, it is inevitable that the nitride film side wall spacers impart stresses to the substrate. While the gate electrode pattern is dry-etched, if the gate insulating film is also removed, the substrate surface is exposed to etching and may be damaged.
A flash memory device is a non-volatile semiconductor memory device which stores information in the form of electric charges in the floating gate electrode. Since the flash memory device has a simple device structure, the flash memory device is suitable for structuring a large scale integrated circuit device.
Information write/erase of a flash memory device is performed by hot carrier injection into the floating gate electrode and carrier extraction by the Fowler-Nordheim tunneling effect. High voltage becomes necessary for such write/erase operations of a flash memory device so that a booster circuit for boosting a power source voltage is formed in a peripheral circuit. Transistors in the booster circuit are required to operate at high voltages.
Recent semiconductor integrated circuits provide a composite function by integrating a flash memory device and a high speed logic circuit on the same substrate. Transistors constituting the high speed logic circuit are required to operate at low voltages. For a high speed operation, it is desired to thin a gate insulating film even if leak current is generated. A circuit operating at a low power dissipation is required in some cases. It is desired to make the gate insulating film thick to some extent in order to reduce leak current for a low power dissipation. In order to meet these requirements, it is desired to form, on the same semiconductor substrate, transistors of a plurality of types having different gate insulating film thicknesses and operating at a plurality of power source voltages.
The retention characteristics of a flash memory cell depend on the charge retaining or holding characteristics of the floating gate electrode. In order to improve the retention characteristics, it is desired to cover the floating gate with an insulating film of good quality. Usually, the lower surface of the floating gate electrode made of a silicon film is covered with a tunneling insulating film, the upper surface thereof is covered with an ONO film, and a thermally oxidized film covers the side walls thereof. The surface of this structure is desired to be covered with a good quality silicon nitride film. The thermally oxidized film is an insulating film with a barrier function for preventing leakage of stored charges, and the silicon nitride film is an insulating film with a barrier function for shielding OH radicals and moisture entering from the external.
Publication JP-A-2003-23114 discloses a method of forming, on the same semiconductor substrate, flash memory cells, low voltage operation transistors and high voltage operation transistors. Side wall spacers are formed at the same time both on the side walls of laminated gate electrodes of flash memory cells and on the side walls of gate electrodes of other transistors.
FIGS. 8A to 8D schematically show an example of a semiconductor device manufacture method of forming at the same time, flash memory cells, low voltage operation transistors and high voltage operation transistors.
As shown in FIG. 8A, the surface of a silicon substrate 11 formed with an isolation region is thermally oxidized to form a tunneling oxide film 25. An amorphous silicon film 26 is deposited on the tunneling oxide film 25, the amorphous silicon film being used later for forming a floating gate. A so-called ONO film 27 constituted of an oxide film 27a, a nitride film 27b and an oxide film 27c is formed on the amorphous silicon film 26. The amorphous silicon film becomes a polysilicon film by later heat treatment.
By using a resist pattern, the ONO film 27 and silicon film 26 are patterned to form a floating gate of a flash memory and an ONO film on the floating gate. At this time, the ONO film and silicon film in the low and high voltage operation transistor areas are completely removed.
By covering the flash memory area with a resist mask, the tunneling oxide film formed on the surface of the transistor area is removed by dilute hydrofluoric acid solution. The resist pattern is removed, and the substrate surface is thermally oxidized to form a thick gate oxide film 13a for high voltage operation transistors.
The flash memory area and high voltage operation transistor area are covered with a resist mask, and the gate oxide film formed on the surface of the low voltage transistor area is removed. After the resist pattern is removed, a thin gate oxide film 13b for low voltage operation transistors is grown by thermal oxidation. In this manner, the thin oxide film and thick oxide film are formed in the transistor area. If gate oxide films having three or more kinds of different thickness are to be formed, similar processes are repeated to form first a thick gate oxide film and then thinner gate oxide films.
Thereafter, a polysilicon film 28 is deposited on the whole substrate surface, and patterned by using a resist mask to form a control gate electrode 28c and gate electrodes 28a and 28b in the transistor area. The surfaces of the silicon films 26 and 28 are thermally oxidized to form a thermally oxidized films 29. By using as a mask at least the gate electrodes formed in this manner, ion implantation for source/drain regions is performed. For example, n-type regions 31, 32 and 33 are formed in the flash memory cell area and extension regions 15 are formed in the transistor area.
As shown in FIG. 8B, a silicon nitride film is deposited on the whole substrate surface by low pressure (LP) CVD, and etched-back to leave side wall spacers 16 only on side walls of the gate electrodes and laminated gate electrode.
As shown in FIG. 8C, the flash memory cell area is covered with a photoresist pattern PR, and ions are implanted into the transistor area to form source/drain regions 17 having a deep junction depth. In this case, the high voltage transistor and low voltage transistor may be separated by resist masks to execute separate ion implantation processes in both the areas.
As shown in FIG. 8D, an interlayer insulating film 21 of silicon oxide or the like is deposited on the substrate formed with the gate electrodes and laminated gate electrode, and contact holes are formed through the interlayer insulating film. A conductive layer is buried in the contact holes, and an unnecessary portion thereof is removed to form conductive plugs 22.
In this manner, it becomes possible to form flash memory cells and transistors of a plurality of types having different gate insulating film thicknesses and different operation voltages.
It is desired for the flash memory cell to have the thermally oxidized film of good quality on the side walls of the laminated gate electrode, and the silicon nitride film 16 of good quality formed by LP-CVD on the thermally oxidized film. In order to form a dense and high quality silicon nitride film, it is desired to execute LP-CVD at a film forming temperature of, e.g., 700° C. or higher.
In the transistor area, the extension regions 15 having a shallow junction depth are already formed before the insulating film having a barrier function such as a silicon nitride film is formed by LP-CVD. As the extension regions are subjected to the heat treatment at 700° C. or higher, impurities are thermally diffused so that there is a possibility that the extension regions cannot retain a desired shape.
In a logic circuit, in order to lower the resistance of the source/drain regions, it is desired to form the silicide layers on the surface of silicon as shown in FIG. 7E. Before the silicide layer is formed, it is necessary to clean the substrate surface with dilute HF solution. In this case, as described in the manufacture processes shown in FIG. 7A to 7E, side-etched recesses are formed under the side wall spacers, forming overhangs. As the overhangs are formed, the overhangs may cause a short circuit and the like.
As above, as semiconductor elements of a plurality of types are formed on the same semiconductor substrate and the characteristics of each semiconductor element are to be optimized, unexpected disadvantages may be given to other semiconductor devices.